past present n future

FW: An Interesting Insight into Decision Making

2007-05-17T09:33:00.001-07:00

Namaskara Baddam sir, Bagunraa, Well that a very interesting story indeed. There are several aspects of it to me: - Developed and Developing Most of the confusion and change in decision making happens in developing countries, developing thoughts, developing tools, developing life, developing situations. But if you see developed countries, developed thoughts, developed tools, and

Software resource and nice psychology paper

2007-05-09T09:16:00.001-07:00

http://www.holub.com/goodies/incompetence.pdfThanks n Regards,-- Bharat

Hardware quick references

2007-05-07T01:20:00.000-07:00

Verilog Quick Referencehttp://www.see.ed.ac.uk/~gateway/Teach/VerilogQuickRef3up2.pdf

Embedded Systems Languages Quick Reference at columbia.edu

2007-05-06T00:10:00.000-07:00

List of my first embedded systems quick reference.http://www1.cs.columbia.edu/~sedwards/classes/2004/emsys-summer/java.9up.pdfhttp://www1.cs.columbia.edu/~sedwards/classes/2004/emsys-summer/assignments.pdfhttp://www1.cs.columbia.edu/~sedwards/classes/2004/emsys-summer/dataflow.9up.pdfhttp://www1.cs.columbia.edu/~sedwards/classes/2004/emsys-summer/systemc.9up.pdfhttp://www1.cs.columbia.edu/~

[IEEE] Auto 3-D stories, Minority report, computer animation

2007-04-05T04:31:00.000-07:00

5. ‘ALICE’ AIMS TO HELP GIRLS BUILD PROGRAMMING SKILLSAlice, a Java-based interactive program that allows users to produce 3-Dcomputer animation images without the need for advanced level programmingskills has been created by a lab director at Carnegie Mellon University(USA) in an effort to draw middle-school age girls to the computer sciencefield. Through the use of a computer mouse, young users

Good quotes from Albert Schweitzer!

2007-03-29T04:18:00.000-07:00

Happiness is nothing more than good health and a bad memory. (or good memory ? Remember good things)!Albert Schweitzer An optimist is a person who sees a green light everywhere, while the pessimist sees only the red stoplight. The truly wise person is colorblind. Albert Schweitzer Anyone who proposes to do good must not expect people to roll stones out of his way, but must accept his lot calmly,

Happy Candlemas Day and Groundhog Day!

2007-02-01T23:48:00.001-08:00

Bharat Singh | rathorebharat

Homeopathy and Avogadro's number, Beyond science!

2007-01-19T05:01:00.001-08:00

Homeopathy's "Law of Infinitesimals"http://www.homeowatch.org/basic/infinitesimals.htmlSensational study of University of Leipzighttp://www.quantec.ch/english/biocommunication/biocommunication_homeopathy_quantec.htmlEvidence profile for the efficacy of homeopathy – A new paradigm for medical sciences:“The Body Information Theory”.http://www.vhan.nl/documents/ScientificReportECHNov04.

Homeopathy and Avogadro's number, Beyond science!

2007-01-19T05:01:00.000-08:00

Logical Puzzle: 4 theifs and black/white hats.

2007-01-17T00:01:00.000-08:00

4 criminals are caught and are to be punished. The Judge allows them to be freed if they can solve a puzzle. If they do not, they will be hung. They agreed.The 4 criminals are lined up on some steps (shown in picture). They are all facing in the same direction. A wall seperates the fourth man from the other three. So to summarise :- Man 1 can see men 2 and 3. Man 2 can see man 3. Man 3 can see

What is EDA? Video! and Others!

2007-01-15T23:17:00.000-08:00

EDA : Nice and simple video!Want to see the electrical signal travelling?http://semizone.stanford.edu/eda/English_low.wmv- Bharat Singh / rathorebharat

What is AMBA Bus? and Experiments on it!

2007-01-12T09:28:00.000-08:00

AMBA bus verification using Vera: Paper from Synopsys.http://www.synopsys.com/designware/docs/vip/amba/latest/doc/apbvipdb.pdf- Bharat Singh / rathorebharat

Testbenches using SystemVerilog

2007-01-12T08:06:00.000-08:00

Book: "SV for Verification" by Chris Spears. recommended by Andreas Zinn!better than "Writing testbenches: using SystemVerilog" by Janick Bergeron.mentor graphics tutorial for SV verification methodology. it accompaniesnice cookbook with small and simple examples too.You will need a password and ID for accessing it.http://www.mentor.com/supportnet/member/tutorials/tutorial.cfm?movie=10192&

SelfDev: Swanson's unwritten rules!

2007-01-09T05:01:00.000-08:00

These were forward to me by Pankaj Singh sometime back:http://sixdisciplines.blogspot.com/2005/10/swansons-unwritten-rules-of-management.htmlGoing over them once in a while, gives you a feeling of unkown satisfaction ;)- Bharat Singh / rathorebharat

Emotional intelligence (EQ) by Burkhard Stubert ;)

2007-01-08T03:47:00.000-08:00

Excerpts from Burkhard Stubert's Letter dated 4th Sept 2006:--------------------------------------------------------------------------There was a story about Tunisian Student; This story pinpoints : emotional intelligence (EQ).I think the student will make his way, because he is emotionallyintelligent - not only rationally intelligent. EQ is a much betterpredictor for future success at school,

EDA: Tutorials Web Seminars Demos: Sharpen the saw

2007-01-07T21:03:00.000-08:00

Some of the demos, web seminars and very good for kick start ;) http://www.demosondemand.com/dod Web seminar on Verification using SystemVerilog and comparison with 'e'.http://www.demosondemand.com/dod/feat_cont/seminars/systverilog.aspx- Bharat Singh / rathorebharat

Specman Verification

2007-01-07T21:02:00.000-08:00

http://www.specman-verification.com/Here you will find lots of basic material about 'e' and specman:Specman TutorialMethodology GuideSpecman And SystemVerilogWork Interview QuestionsSpecman 'E' reference cardwww.geocities.com/deepakgeorge2000/vlsi_book/quick_reference4.0.4.pdfUnderstanding the "e" verification language: By it's creators:http://www.eetimes.com/story/OEG20030529S0072Other

SelfDev: Rudyard Kipling

2007-01-02T03:04:00.000-08:00

Very interesting prose; about life by Rudyard Kipling.....If you can keep your head when all about you Are losing theirs and blaming it on you, If you can trust yourself when all men doubt you, But make allowance for their doubting too... If you can talk with crowds and keep your virtue, Or walk with Kings — nor lose the common touch, If neither foes nor loving friends can hurt you, If all

Clearcase verses others?

2006-12-08T08:21:00.000-08:00

http://svn.haxx.se/users/archive-2005-07/0287.shtml- Bharat Singh | rathorebharat

When real mux is infered by synthesis?

2006-12-07T07:11:00.000-08:00

with SEL select DOUT <= DI_SCAN when '1', DIN when others;Or a case statementcase SEL is begin when '1' => DOUT <= DI_SCAN; when '0' => DOUT <= DIN; when others => DOUT <= '0';end case;What could be the probelm with if/else;mux_scan: process(DI_SCAN, DIN, SEL) begin if (SEL = '1') begin DOUT <= DI_SCAN; else DOUT <= DIN; end if;end process;- Bharat Singh |

Create a set latch from a reset latch?

2006-12-05T06:55:00.000-08:00

- Bharat Singh | rathorebharat

What are JTAGs? using Boundary scans?

2006-12-04T07:32:00.000-08:00

Simple definitions or concepts:http://en.wikipedia.org/wiki/JTAGhttp://en.wikipedia.org/wiki/Boundary_scanhttp://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-intro.htmlNice manual about JTAG + DFT from Texas Instrumenthttp://www.xess.com/faq/M0000297.HTMhttp://focus.ti.com/lit/an/ssya002c/ssya002c.pdfmore details and interesting facts later....- Bharat Singh | rathorebharat

Lock up latches? Common uses?

2006-12-04T07:23:00.000-08:00

Stitching of multiple scan chains. (multiple clock domains).(different clock enable, posedge, negedge).Automatically generated by the Test compiler for scan chains.10 tips for successful scan design: part one & two - 2/17/2000 - EDNhttp://www.edn.com/article/CA46603.htmlhttp://www.edn.com/article/CA46604.html www.evaluationengineering.com/archive/articles/0997dft.htm-- Bharat Singh | rathorebharat

HW:Launch and capture shift clocks for delay tests? double pulse?

2006-12-04T06:58:00.000-08:00

This concept is used for finding transition delay (rise fall) faults:http://www.soccentral.com/results.asp?CatID=488&EntryID=13069This explains the basics of launch capture and double pulse:http://www.iec.org/events/2005/euro_designcon/pdf/6-ta1.pdfSlow speed clock is required to launch (load unload) the scan flopsor chains and then the faster PLL clock is used generate 2 or 3pulses of at-speed

How to make multiple chains work effectively?

2006-12-04T06:46:00.000-08:00

Need of compression logic for scan. EDT compactor.Collectively feeding multiple scan chains in the design.For basics:www.mentor.com/products/dft/news/articles/upload/06_TM_test_compression.pdfAdvanced stuff:www.mentor.com/products/dft/upload/ITC2005_Compressed_Pattern_Diagnosis_30_3.pdfMore test strategies for testing memories:http://www.elecdesign.com/Articles/Print.cfm?ArticleID=9527Multiple

SD:Where British and French management differ?

2006-11-24T01:48:00.001-08:00

A amulgam of good traits of all management styles is being Roman in Rome.Excerpts from the below article on internet.http://www.mngt.waikato.ac.nz/ejrot/cmsconference/2005/proceedings/criticalresearch/Boussebaa.pdfUpon 'colonizing' firms, the former become cadres. The term 'cadre' originated from the military and, at the beginning of industrialisation, the French firm hierarchy model presented

SD:Does Science and Spirituality Converge at 'c' (Speed of Light)?

2006-11-24T01:28:00.001-08:00

More story to come later.- Bharat Singh | Prashanth | rathorebharat

HW: Remove a component or module from the chip hierarchy?

2006-11-23T00:05:00.001-08:00

Any declaration of that component or module should be removed.Any instantiation of them should be removed. All remaining holesfor the signals travelling should be highlighted.This task is a bit tedious and complex as it needs to be done atchip level.Thanks n Regards,-- Bharat Singh | rathorebharat

SelfDev: Do you differentiate right and left brain?

2006-11-16T07:36:00.000-08:00

Right brain programming Left and right brain quiz Ask.com: Right Brain / Left Brain: What Is It All About? Ask.com: Right Brain / Left Brain Quiz for Artists - Bharat Singh | rathorebharat

HW: Find finer points to verify this simplest protocol?

2006-11-15T08:46:00.000-08:00

Ready comes within 4 clock cycles.Should not miss more than 2 write enables.Write 'e' transactions or tests for the same.Write formal verification properties.Write VHDL or VERILOG testcases.- Bharat Singh | rathorebharat

HW: Device best solution for 32bit and 64bit restricted interface! (VHDL)

2006-11-15T07:41:00.000-08:00

We have a entity or module which has input output interfaceof 32bit wide word. This entity or module will instantiate amemory of 64bit word. Now device best VHDL solution to feed andreceive this 64bit memory using this 32bit restricted interface.What will be impact on the highest possible speed which this64bit memory can possibly be used.Analyze both the cases when input and ouput interface can

Where an SOC consumes power?

2006-11-15T05:15:00.000-08:00

Accurate power-analysis techniques support smart SOC-design choices Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort Sequense power aware SoC design flow Power Islands: The Evolving Topology of SoC Power Management - Bharat Singh | rathorebharat

Algorithms used by BIST? Marching? Others?

2006-11-15T05:03:00.000-08:00

- Bharat Singh | rathorebharat

Best book for Beginners for VHDL Verilog and Sysnthsis under one Roof?

2006-11-14T07:27:00.000-08:00

Douglas Smith (One of the best books) Golden referenceHDL Chip Design : A Practical guide for Designing, Synthesizing andSimulating ASICs and FPGAs using VHDL or Verilogby Douglas J. SmithPublication date: June 1st 1996 http://www.amazon.com/Hdl-Chip-Design-Synthesizing-Simulating/dp/0965193438- Bharat Singh | rathorebharat

How to migrate from 'e' to SystemVerilog?

2006-11-14T07:19:00.001-08:00

Synopsys Verification Avenuehttp://www.synopsys.com/news/pubs/veritb/oct06/va_vol6_iss3_f6.pdfOrhttp://www.synopsys.com/cgi-bin/systemverilog/pdfr1.cgi?file=SystemVerilog_for_e_Experts_Janick_Bergeron.pdfOrhttp://www.synopsys.com/links/va_oct06.html?BAC-va&Link=Oct06_Issue_SNPS_Home_PubsOrEE Times: SystemVerilog won't kill 'e,' say proponentshttp://www.eetimes.com/showArticle.jhtml?articleID=

What are HDFR in memories? Uses?

2006-11-14T07:00:00.001-08:00

[HW] What is meant by scrabling in memories?

2006-11-14T06:59:00.001-08:00

What are ring osillators? Their Common Uses?

2006-11-14T06:55:00.001-08:00

What are BFMs?

2006-11-12T23:10:00.001-08:00

History: Reference: http://www.simpod.com/registered/powerpc-bfm.pdfThe BFM came into existence when FPGAs and ASICs started to interface to other chips forwhich a complete, full-functional model was too complex or not available. Engineers realizedthat the behavior of devices was less important and what really counts is what happens on thepins of a chip. A bus functional model is a model that

Difference between Testbench and Testcase?

2006-11-12T23:09:00.000-08:00

History: Reference: http://www.eetimes.com/editorial/1995/hdlcolumn9504.htmlMore than one engineer has wondered where this silly word came from and why in the world anyone would use it to describe simulation control models. While the real origin of the term is lost, at least to us, the first we remember hearing it was back in the early days of VHDL when it was used by the original VHDL

Minimun circuit Disk rotation (Jerome).

2006-11-12T23:06:00.000-08:00

Hello Everyone,This question was from Jerome sometime back.If I have a circular disk painted half in black and white. Now I have two sensor each one of them produces 1 and 0 when it is under (or detects) black and white region of the disk respectively. Now place the sensor anywhere under the disk and give me the smallest circuit (with Minimum digital components) to find if the disk is rotating

Agile 2006: Another Perspective/Story

2006-07-25T23:32:00.000-07:00

On a beautiful Friday morning when I drove to this Agile 2006 conference in extreme corner of Bangalore,I imagined beautiful Bangalore without those traffic problems. Here are my experiences for sharing:An eye opener!A wonderful story, that put forth a platform for many more stories!A product development seminar : A story teller's way!Reminds about Stefan Covey's habit "WIN WIN" & Cirle of