Specman Verification

http://www.specman-verification.com/

Here you will find lots of basic material about 'e' and specman:

Specman Tutorial
Methodology Guide

Specman And SystemVerilog
Work Interview Questions

Specman 'E' reference card
www.geocities.com/deepakgeorge2000/vlsi_book/quick_reference4.0.4.pdf


Understanding the "e" verification language: By it's creators:
http://www.eetimes.com/story/OEG20030529S0072

Other references are:

Specman documents coming with Specman.
/opt/specman_5.1/docs/SpecmanDocs/VerisityHelp.htm

Books:

Design Verification with 'e' by Samir Parnitkar.

Small memory eVC example in Cadence Incisive newsletter.
http://www.cadence.com/newsletters/incisiveplatform/Incisive_Specman.pdf?CMP=EMC-4NJ239202048

SystemVerilog for e Experts: Understanding the Migration Processhttp://www.techonline.com/learning/webinar/200010

A fresh spereation of contents: Good paper!http://www.cadence.com/whitepapers/e_aspect.pdf

- Bharat Singh | rathorebharat