This concept is used for finding transition delay (rise fall) faults:
http://www.soccentral.com/results.asp?CatID=488&EntryID=13069
This explains the basics of launch capture and double pulse:
http://www.iec.org/events/2005/euro_designcon/pdf/6-ta1.pdf
Slow speed clock is required to launch (load unload) the scan flops
or chains and then the faster PLL clock is used generate 2 or 3
pulses of at-speed of internal clock (given to scan flops). The data
is then compared. This is the delay test for the chip.
Nice PPT about delay tests with scan (some algorithms).
www.eng.auburn.edu/~xugefu1/D&TSeminar/files/VLSI07.ppt
At-Speed Structural Test:
ieeexplore.ieee.org/iel5/6540/17459/00805810.pdf
- Bharat Singh | rathorebharat
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