When real mux is infered by synthesis?

with SEL select
DOUT <= DI_SCAN when '1',
DIN when others;

Or a case statement

case SEL is
begin
when '1' => DOUT <= DI_SCAN;
when '0' => DOUT <= DIN;
when others => DOUT <= '0';
end case;

What could be the probelm with if/else;

mux_scan: process(DI_SCAN, DIN, SEL)
begin
if (SEL = '1') begin
DOUT <= DI_SCAN;
else
DOUT <= DIN;
end if;
end process;

- Bharat Singh | rathorebharat