SD:Where British and French management differ?

A amulgam of good traits of all management styles is being Roman in Rome.

Excerpts from the below article on internet.
http://www.mngt.waikato.ac.nz/ejrot/cmsconference/2005/proceedings/criticalresearch/Boussebaa.pdf

Upon 'colonizing' firms, the former become cadres. The term 'cadre' originated from the military and, at the beginning of industrialisation, the French firm hierarchy model presented strong similarities with that of the French army (Poirson, 1993: 54).

The term 'cadre' denotes the dominating managerial class, and althoug h graduates from the university system may also establish themselves as cadres, they lack the status and authority of the graduates of the Grandes Écoles. The term 'cadre' differs from the Anglo-Saxon term 'manager' in that the latter focuses on the management of people whereas the former has a more strategic, planning role (Gordon, 1996).

http://www.mngt.waikato.ac.nz/ejrot/cmsconference/2005/proceedings/criticalresearch/Boussebaa.pdf

French management tends to
conform to Trompenaar's (1993) 'Eiffel Tower' model of corporate organisation, whereby French firms tend to be hierarchical, with a rigid, bureaucratic and well-defined division of labour imposed by the upper echelons of the hierarchy (see also Hofstede 1980). State dirigisme is reflected in management in that the latter is characterised by a centralisation of decision-making that is unquestioned, attaching great importance to the principle of the 'Unity of Command' (Fayol, 1970). Thus, French management is based on the principle of control with power concentrated at the top of the hierarchy (Lane, 1994; van der Klink and Mulder, 1995). Cadres are viewed as autocratic, directive. They see the firm as an elite school in which they are the most intelligent and subordinates, therefore, cannot conceivably have valid ideas. Cadres are, therefore, more possessive of their individual autonomy. Their reaction is: "I know my job; if I am controlled, this means they have no confidence in me" (Poirson, 1993). In contrast, British managers attach less importance to being authoritarian and hence have a more participative, democratic managerial style (Lane, 1989: ch. 4).

http://www.mngt.waikato.ac.nz/ejrot/cmsconference/2005/proceedings/criticalresearch/Boussebaa.pdf

Accor: Story of the merger of american and french company

Franck's book details many other experiences in addition to that of Rhone Poulenc. One of the
successes is that of Accor, the hotel chain. It initially got itself into a bad situation by offering the managers of Motel 6, the company it bought out, a handsome benefits package based on maintaining quarterly and yearly profits over a three-year period, by which time the managers on board at the time of acquisition would leave the company. Introducing a theme which runs throughout the book, Franck details this example of "moral hazard" : the American managers of Motel 6 immediately stopped managing in the interests of the shareholder and ran the company solely to increase short-term bottom-line profits to reward themselves with the highest possible bonuses. Capital investment came to a halt, preventive maintenance vanished, rooms were no longer redecorated. In fact, in many motels, the rooms were no longer even swept or cleaned. Regular clients began to prefer to sleep in their cars in the parking lot when faced with the alternative of a louse and rat-ridden room in a Motel 6 which had become known as a hang-out for drug-dealers.

When Accor realised what was happening they sent Georges Le Mener to turn the situation around. He had come to them after leaving vocational school with only a flimsy hotel management certificate. However he had later graduated with honors from the internal Accor training system, one of the best in France. As Guillaume Franck writes in his book, Le Mener arrived at Motel 6 knowing he had confidence in himself, but knowing precious little about the U.S. and even less about the American budget hotel market. He succeeded against all odds. In making a success of Motel 6, Le Mener handsomely paid back the training and confidence Accor senior management had vested in him. Without him Accor would never have made another acquisition in the U.S., but because of him they later purchased Red Roof Inns and they now have more than 10% of the budget hotel market in the U.S.

Accor brings its managers up through a tough corporate university just outside Paris in which the client is king. The company recruits its staff from outside the elite French management schools (les grandes écoles). Pechiney, on the other hand, used the old boy network to a maximum. Pechiney bought American Can in a famously corrupt deal and is a perfect example of all that can go wrong with the French management style. Le Mener bore more of a resemblance to the typical American manager than to any other French manager mentioned in the book. Many of the other French managers mentioned were incapable of functioning six thousand miles away from their "grande école" support networks and they had to be ignominiously repatriated, in a number of cases because their American subordinates
and colleagues perceived so much arrogance that they just couldn't work with them.

- Bharat Singh | rathorebharat

SD:Does Science and Spirituality Converge at 'c' (Speed of Light)?

More story to come later.

- Bharat Singh | Prashanth | rathorebharat

HW: Remove a component or module from the chip hierarchy?

Any declaration of that component or module should be removed.
Any instantiation of them should be removed. All remaining holes
for the signals travelling should be highlighted.
This task is a bit tedious and complex as it needs to be done at
chip level.

Thanks n Regards,


-- Bharat Singh | rathorebharat

SelfDev: Do you differentiate right and left brain?

Right brain programming
Left and right brain quiz
Ask.com: Right Brain / Left Brain: What Is It All About?

Ask.com: Right Brain / Left Brain Quiz for Artists

- Bharat Singh | rathorebharat

HW: Find finer points to verify this simplest protocol?

Ready comes within 4 clock cycles.
Should not miss more than 2 write enables.

Write 'e' transactions or tests for the same.
Write formal verification properties.
Write VHDL or VERILOG testcases.

- Bharat Singh | rathorebharat

HW: Device best solution for 32bit and 64bit restricted interface! (VHDL)

We have a entity or module which has input output interface
of 32bit wide word. This entity or module will instantiate a
memory of 64bit word. Now device best VHDL solution to feed and
receive this 64bit memory using this 32bit restricted interface.

What will be impact on the highest possible speed which this
64bit memory can possibly be used.

Analyze both the cases when input and ouput interface can be
inout or (only input and only output).

What logic needs to be added in between the interface
and the memory?

- Bharat Singh | rathorebharat

Where an SOC consumes power?

Accurate power-analysis techniques support smart SOC-design choices

Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort

Sequense power aware SoC design flow

Power Islands: The Evolving Topology of SoC Power Management

- Bharat Singh | rathorebharat

Algorithms used by BIST? Marching? Others?

- Bharat Singh | rathorebharat

Best book for Beginners for VHDL Verilog and Sysnthsis under one Roof?

Douglas Smith (One of the best books) Golden reference

HDL Chip Design : A Practical guide for Designing, Synthesizing and
Simulating ASICs and FPGAs using VHDL or Verilog

by Douglas J. Smith
Publication date: June 1st 1996

http://www.amazon.com/Hdl-Chip-Design-Synthesizing-Simulating/dp/0965193
438

- Bharat Singh | rathorebharat

How to migrate from 'e' to SystemVerilog?

Synopsys Verification Avenue
http://www.synopsys.com/news/pubs/veritb/oct06/va_vol6_iss3_f6.pdf
Or
http://www.synopsys.com/cgi-bin/systemverilog/pdfr1.cgi?file=SystemVeril
og_for_e_Experts_Janick_Bergeron.pdf
Or
http://www.synopsys.com/links/va_oct06.html?BAC-va&Link=Oct06_Issue_SNPS
_Home_Pubs
Or
EE Times: SystemVerilog won't kill 'e,' say proponents
http://www.eetimes.com/showArticle.jhtml?articleID=174400218&printable=t
rue

- Bharat Singh | rathorebharat

What are HDFR in memories? Uses?

[HW] What is meant by scrabling in memories?

What are ring osillators? Their Common Uses?

What are BFMs?

History: Reference: http://www.simpod.com/registered/powerpc-bfm.pdf
The BFM came into existence when FPGAs and ASICs started to interface to other chips for
which a complete, full-functional model was too complex or not available. Engineers realized
that the behavior of devices was less important and what really counts is what happens on the
pins of a chip. A bus functional model is a model that provides a task or procedural interface
to specify certain bus operations for a defined bus protocol. For microprocessors these
transactions usually take the form of read and write operations on the bus. Bus functional
models are easy to use and provide good performance. Unfortunately, BFM accuracy is only
as good as the engineer who wrote it and the data book used to write it. The challenge facing
new projects is where to get bus models and how to guarantee they are accurate.
New methods for model creation are needed that can provide all the benefits of the BFM
without the accuracy problems and the increasing model creation times. (Ref1)
The choice of what kinds of models to use for design verification depends on the skill set and
experience of the engineers involved. Many engineers prefer to write the tests in C and run them
on the target microprocessor. This results in a set of system diagnostics that can then be run on
the final product in the lab. Other engineers who are not familiar with C or assembly language
and do not want to understand how to initialize a microprocessor tend to use bus functional
models to verify system operation. Ease of use and good performance make bus models
attractive for testbench development for ASIC and board simulation. As bus protocols get more
and more complex new techniques for bus model creation and validation are required. One
solution to this problem is to use a hardware modeler to provide the functionality and features of a
bus model. Using a hardware model as a bus model provides the best accuracy, takes the least
time to develop, and has many other uses including full-functional models and HW/SW coverification.
Reference: http://www.simpod.com/registered/powerpc-bfm.pdf

"V) High Level Verification
Reference: http://www.deepchip.com/posts/bsnug00.html

e Reuse Methodology (eRM) Developer Manual
This really takes a very good example and explains the role of BFM is the verification evironment.
4 Typical eVC Architecture
4.1 Basic eVC Architecture
4.1.1 DUT and eVC
4.1.1 DUT and eVC
BFM
Bus Functional Model-- a unit instance that interacts with the DUT and both drives and samples the DUT signals.
Monitor
A unit instance that passively monitors (samples) the DUT signals and supplies interpretation of the monitored activity to the other components of the agent. Monitors can emit events when they notice interesting things happening in the DUT or on the DUT interface. They can also check for correct behavior or collect coverage.
In Figure 4-2, notice that the BFMs have bidirectional arrows to the DUT. This signifies the fact that they can both drive and sample DUT signals. Monitors have unidirectional arrows pointing from the DUT to them. This signifies that they can only sample data from the DUT. Monitors cannot drive DUT signals.

In the XSerial protocol, the XSerial eVC could have two agents-- an RX agent and a TX agent-- where the RX agent is significantly more simple than the TX agent. If the flow control mechanism involves a high level of interaction between the two directions, implement a single-agent eVC to model the flow control mechanism efficiently. The single agent covers both the TX and RX directions. The single agent contains all of the monitors, BFMs, and sequence drivers required for both directions.
4.1.1.1 Diagram Language
file:///opt/specman_5.1/components/sn/docs/online_help/wwhelp/wwhimpl/js/html/wwhelp.htm
5.1 Introduction to SequencesSequences let you define streams of data items sent to a DUT (or streams of actions performed on a DUT interface). You can also use sequences to generate static lists of data items with no connection to a DUT interface.
Sequence Driver
A unit that serves as the mediator between the sequences and the verification environment. The generated items are passed from the sequence to the sequence driver and the sequence driver acts upon them one by one, typically passing them to some kind of BFM (Bus Functional Model). Of course, the sequence driver can be rather empty and, instead of driving items into the DUT, simply place them on a list.
To complete the picture:
* A TCM does the actual driving of items into a specific DUT channel.
* The TCM resides in a BFM unit.
* For the purpose of driving data into the DUT, the sequence driver interacts only with the BFM.
The sequence driver and the BFM work as a pair, where the sequence driver serves as the interface upwards towards the sequences so that the sequences can always see a standard interface to the DUT. The BFM serves as the interface downwards to the DUT, letting you write sequences in any way you find appropriate.
At first, it might seem unnecessary to separate the sequence driver and the BFM. The importance of this separation becomes clear when implementing virtual sequences (see "Using Virtual Sequences").
The execution flow for generation of items and driving them into the DUT is as follows:
* The sequence driver launches the main TCM of a sequence (called body()), which in turn launches the main TCM of any subsequences. (See "Defining the Behavior of Sequences".)
* Sequences generate items on the fly (as part of the execution of their body() TCM).
* Each generated item is passed to the sequence driver, which in turn passes it to the BFM.
file:///opt/specman_5.1/components/sn/docs/online_help/wwhelp/wwhimpl/js/html/wwhelp.htm
Verilog examples of real BFMs.
http://www.gateslinger.com/chiphead/snug99_vbfm.pdf
BFM and reuse:
http://www.us.design-reuse.com/articles/article5164.html
Examples:
Course on web:
http://webcourse.cs.technion.ac.il/236605/Spring2006/
Exercises:
http://webcourse.cs.technion.ac.il/236605/Spring2006/hw/WCFiles/HW2.PDF
Books:
Misc:
Personal experience:

Difference between Testbench and Testcase?

History: Reference: http://www.eetimes.com/editorial/1995/hdlcolumn9504.html
More than one engineer has wondered where this silly word came from and why in the world anyone would use it to describe simulation control models. While the real origin of the term is lost, at least to us, the first we remember hearing it was back in the early days of VHDL when it was used by the original VHDL development team to refer to VHDL models that controlled the simulation of other VHDL models. To explain the word (and cement the analogy in the process) there was even a picture in a manual showing a work bench with waveform generator boxes driving the inputs to a "VHDL model" and oscilloscopes attached to the outputs.
Some may argue that in spite of the obvious analogy, it's still a silly word to use. We think the truth of the matter is that the word "testbench" has caught on for one simple reason: the lack of a better word. While "testbench" doesn't have any sex appeal, it also doesn't have any competition. Which slips off your tongue more easily: "simulation control model" or "testbench?" What other choices are there? And just to mark its acceptance into EDA jargon, let us point out that the word testbench has now broken the bonds of its VHDL heritage and has quietly slipped into the idiom of the Verilog world.
What's a testbench? In order to test the model of some design, a designer must apply test patterns to the input ports and observe the output ports over time to decide whether the inputs were transformed to the expected outputs. The model is generally referred to as the design under test (DUT). By testing, we mean verifying functional correctness, not finding manufacturing faults. The most common method used to accomplish this is to physically surround the DUT with a layer of code that performs the stimulus generation and output comparison (see Figure 1). This layer of code, known as a testbench, can be very simple or as complex as necessary for the application at hand.
Although testbench code has traditionally been coded using a simulator-specific simulation control language, we are going to recommend highly that the testbench be written using the same language as the DUT, whether VHDL or Verilog. The reason is simple: model transportability. These days, very few design models can be expected to spend their entire existence running on the same simulator. Sooner or later they are going to be sent across the street or across the country to some other group that uses a different simulator. If the testbench can't make the trip along with the DUT, a critical analysis capability has been totally lost.
Generally, the testbench is created as a new hierarchical level by defining a VHDL entity/architecture pair or a Verilog HDL module with no ports, one or more instances of the DUT and arbitrarily structured pieces of code to generate and apply test patterns and observe results. All of these code fragments are interconnected via signals. This new hierarchical level is frequently named (or referred to as) system, top, test, testbench, or environment.
The term "testbench" is somewhat generic in that it generally includes all the stimulus generation and output comparison applied to some DUT. Some unique set of input stimuli created to test a unique operation of the DUT is referred to as a test case, and one input vector from the test case is usually called a test pattern. A reference to a DUT's testbench is generally considered a reference to all the test patterns in all the test cases associated with that DUT.
Reference: http://www.eetimes.com/editorial/1995/hdlcolumn9504.html

Verification flow starts with understanding the specification of the chip/block under verification. Once the specification is understood, a test cases document is prepared, which documents all possible test cases. Once this document is done to a level where 70-80 percent functionality is covered, a testbench architecture document is prepared. In the past, this document was prepared first and the test cases one was prepared next. There is a drawback with this style: if test cases document shows a particular functionality to be verified and if testbench does not support it, as the architecture document was prepared before the test cases one. If we have a test cases document to refer to, then writing an architecture document becomes much easier, as we know for sure what is expected from the testbench.
Test Cases
Identify the test cases from the design specification: a simple task for simple cases. Normally requirement in test cases becomes a test case. Anything that specification mentions with "Can do", "will have" becomes a test case. Corner test cases normally take lot of thinking to be identified.
Testbench Architecture
Typical testbench architecture looks as shown below. The main blocks in a testbench are base object, transaction generator, driver, monitor, checker/scoreboard.
The block in red is the DUT, and boxes in orange are the testbench components. Coverage is a separate block which gets events from the input and output monitors. It is the same as the scoreboard, but does something more.
Referrence: http://www.asic-world.com/tidbits/typical_verification.html
Books:
Exercises/Examples:
http://www.asic-world.com/verilog/art_testbench_writing3.html
Misc:
Personal experience: ;(
Thanks n Regards,
-- Bharat

Minimun circuit Disk rotation (Jerome).

Hello Everyone,
This question was from Jerome sometime back.If I have a circular disk painted half in black and white. Now I have two sensor each one of them produces 1 and 0 when it is under (or detects) black and white region of the disk respectively. Now place the sensor anywhere under the disk and give me the smallest circuit (with Minimum digital components) to find if the disk is rotating clockwise or anticlockwise.PS: When sensor in under white region it produces output 0 and when it is under black it produces 1
Thanks n Regards,-- Bharat