Clearcase verses others?

http://svn.haxx.se/users/archive-2005-07/0287.shtml

- Bharat Singh | rathorebharat

When real mux is infered by synthesis?

with SEL select
DOUT <= DI_SCAN when '1',
DIN when others;

Or a case statement

case SEL is
begin
when '1' => DOUT <= DI_SCAN;
when '0' => DOUT <= DIN;
when others => DOUT <= '0';
end case;

What could be the probelm with if/else;

mux_scan: process(DI_SCAN, DIN, SEL)
begin
if (SEL = '1') begin
DOUT <= DI_SCAN;
else
DOUT <= DIN;
end if;
end process;

- Bharat Singh | rathorebharat

Create a set latch from a reset latch?

- Bharat Singh | rathorebharat

What are JTAGs? using Boundary scans?

Simple definitions or concepts:
http://en.wikipedia.org/wiki/JTAG
http://en.wikipedia.org/wiki/Boundary_scan
http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-intro.html

Nice manual about JTAG + DFT from Texas Instrument
http://www.xess.com/faq/M0000297.HTM
http://focus.ti.com/lit/an/ssya002c/ssya002c.pdf

more details and interesting facts later....

- Bharat Singh | rathorebharat

Lock up latches? Common uses?

Stitching of multiple scan chains. (multiple clock domains).
(different clock enable, posedge, negedge).

Automatically generated by the Test compiler for scan chains.

10 tips for successful scan design: part one & two - 2/17/2000 - EDN
http://www.edn.com/article/CA46603.html
http://www.edn.com/article/CA46604.html

www.evaluationengineering.com/archive/articles/0997dft.htm

-- Bharat Singh | rathorebharat

HW:Launch and capture shift clocks for delay tests? double pulse?

This concept is used for finding transition delay (rise fall) faults:
http://www.soccentral.com/results.asp?CatID=488&EntryID=13069

This explains the basics of launch capture and double pulse:
http://www.iec.org/events/2005/euro_designcon/pdf/6-ta1.pdf

Slow speed clock is required to launch (load unload) the scan flops
or chains and then the faster PLL clock is used generate 2 or 3
pulses of at-speed of internal clock (given to scan flops). The data
is then compared. This is the delay test for the chip.

Nice PPT about delay tests with scan (some algorithms).
www.eng.auburn.edu/~xugefu1/D&TSeminar/files/VLSI07.ppt

At-Speed Structural Test:
ieeexplore.ieee.org/iel5/6540/17459/00805810.pdf

- Bharat Singh | rathorebharat

How to make multiple chains work effectively?

Need of compression logic for scan. EDT compactor.
Collectively feeding multiple scan chains in the design.

For basics:
www.mentor.com/products/dft/news/articles/upload/06_TM_test_compression.pdf

Advanced stuff:
www.mentor.com/products/dft/upload/ITC2005_Compressed_Pattern_Diagnosis_30_3.pdf

More test strategies for testing memories:
http://www.elecdesign.com/Articles/Print.cfm?ArticleID=9527

Multiple short scan chains could be connected to single
big scan chain. Only care is required to see if the connection
is done to correct edge triggered scans. Output of one scan chains
becomes input of another scan chain.

Multiple clock domains might require lockup latches for connecting
mutiple smaller scan chains to one scan chain

- Bharat Singh | rathorebharat