past present n future

Blog Archive

  • ►  2007 (18)
    • ►  May (4)
      • FW: An Interesting Insight into Decision Making
      • Software resource and nice psychology paper
      • Hardware quick references
      • Embedded Systems Languages Quick Reference at colu...
    • ►  April (1)
      • [IEEE] Auto 3-D stories, Minority report, computer...
    • ►  March (1)
      • Good quotes from Albert Schweitzer!
    • ►  February (1)
      • Happy Candlemas Day and Groundhog Day!
    • ►  January (11)
      • Homeopathy and Avogadro's number, Beyond science!
      • Homeopathy and Avogadro's number, Beyond science!
      • Logical Puzzle: 4 theifs and black/white hats.
      • What is EDA? Video! and Others!
      • What is AMBA Bus? and Experiments on it!
      • Testbenches using SystemVerilog
      • SelfDev: Swanson's unwritten rules!
      • Emotional intelligence (EQ) by Burkhard Stubert ;)...
      • EDA: Tutorials Web Seminars Demos: Sharpen the saw...
      • Specman Verification
      • SelfDev: Rudyard Kipling
  • ▼  2006 (24)
    • ►  December (7)
      • Clearcase verses others?
      • When real mux is infered by synthesis?
      • Create a set latch from a reset latch?
      • What are JTAGs? using Boundary scans?
      • Lock up latches? Common uses?
      • HW:Launch and capture shift clocks for delay tests...
      • How to make multiple chains work effectively?
    • ▼  November (16)
      • SD:Where British and French management differ?
      • SD:Does Science and Spirituality Converge at 'c' (...
      • HW: Remove a component or module from the chip hie...
      • SelfDev: Do you differentiate right and left brain...
      • HW: Find finer points to verify this simplest prot...
      • HW: Device best solution for 32bit and 64bit restr...
      • Where an SOC consumes power?
      • Algorithms used by BIST? Marching? Others?
      • Best book for Beginners for VHDL Verilog and Sysnt...
      • How to migrate from 'e' to SystemVerilog?
      • What are HDFR in memories? Uses?
      • [HW] What is meant by scrabling in memories?
      • What are ring osillators? Their Common Uses?
      • What are BFMs?
      • Difference between Testbench and Testcase?
      • Minimun circuit Disk rotation (Jerome).
    • ►  July (1)
      • Agile 2006: Another Perspective/Story

GMT + 5:30 : IST

Favourite Links

  • EDA: John Cooley: Tools, Reviews, Comparision
  • SW: Guru of the week (C++ topics)
  • HW: Phil Moorby:
  • Hardware Specification and Verification Home CIS 410/510
  • HW: Janick Bergeron
  • Spiritual: Bhagavad-Gita Org
  • HW: Gordon E Moore: Father of Intel
  • HW: Jack S Kilby: Father of Integrated Circuit
  • WGBH Forum Network | Free Online Lectures
  • Free Online Education
  • Edu: MIT Master Course List
  • History
  • Mathematics
  • Physics
  • SW: James Gosling - Father of Java
  • SW: Andrei Alexandrescu Modern C++ Design
  • SW:Josuttis Vandevoorde C++ Templates
  • SW: Robert C Martin : Object Mentor
  • Agile: SCRUM Ken Schwaber
  • Leadership: Ken Blanchard
  • SelfDev: Mind Mapping Tool
  • News: EEtimes
  • News: EDA career cafe
  • News: EDA cafe
  • Agile: Alistair Cockburn
  • Agile: Kent Beck: XP
  • Mentor: Burkhard Stubert
  • EDA: Aart de Geus
  • SelfDev: STEPHEN R. COVEY
  • SW: Thomas H. Cormen: Algorithm
  • Misc: Albert Einstein Online
  • Agile: Craig Larman's: Father of Agile
  • Agile: Martin Fowler: Refactoring
  • SW: Bjarne Stroustrup's: Father of C++
  • HW: EETimes Design Lines
  • Fun: Wikepedia Main Page
  • EDA: Free HDL-vhdl Simulator
  • IITK Robotics BRIcKs
  • Fun: Brain ashers Puzzles
  • SW: Robert Sedgewick: Algorithms: Princeton
  • SW: Introduction to CS and Java Prog: Robert Sedgewick
  • SelfDev: Career Skill Resource
  • Free Tata Macgraw Hill books online
  • SW: Methods and Tool for SW and Test
  • SW: Qt Tutorial
  • Fun: James Randi: Paranormal PsuedoScientfic Supernatural
  • Kids: Arvind Toys and Books
  • Kids: Preschool at home
  • Kids: Fun Learning to read
  • News: Google News

Contributors

  • Prashanth Goud
  • bharat
  • Gaggu
  • Abhijit

Wednesday, November 15, 2006

Where an SOC consumes power?

Accurate power-analysis techniques support smart SOC-design choices

Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort

Sequense power aware SoC design flow

Power Islands: The Evolving Topology of SoC Power Management

- Bharat Singh | rathorebharat
Posted by bharat at 5:15 AM

0 comments:

Post a Comment

Newer Post Older Post Home
Subscribe to: Post Comments (Atom)