Friday, January 12, 2007

Testbenches using SystemVerilog

Book: "SV for Verification" by Chris Spears. recommended by Andreas Zinn!

better than "Writing testbenches: using SystemVerilog" by Janick Bergeron.

mentor graphics tutorial for SV verification methodology. it accompanies
nice cookbook with small and simple examples too.
You will need a password and ID for accessing it.

http://www.mentor.com/supportnet/member/tutorials/tuto
rial.cfm?movie=10192&snw_source=CAMP86


- Bharat Singh / rathorebharat

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