Friday, December 08, 2006

Thursday, December 07, 2006

When real mux is infered by synthesis?

with SEL select
DOUT <= DI_SCAN when '1',
DIN when others;

Or a case statement

case SEL is
begin
when '1' => DOUT <= DI_SCAN;
when '0' => DOUT <= DIN;
when others => DOUT <= '0';
end case;

What could be the probelm with if/else;

mux_scan: process(DI_SCAN, DIN, SEL)
begin
if (SEL = '1') begin
DOUT <= DI_SCAN;
else
DOUT <= DIN;
end if;
end process;

- Bharat Singh | rathorebharat

Tuesday, December 05, 2006

Create a set latch from a reset latch?

- Bharat Singh | rathorebharat

Monday, December 04, 2006

What are JTAGs? using Boundary scans?

Simple definitions or concepts:
http://en.wikipedia.org/wiki/JTAG
http://en.wikipedia.org/wiki/Boundary_scan
http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-intro.html

Nice manual about JTAG + DFT from Texas Instrument
http://www.xess.com/faq/M0000297.HTM
http://focus.ti.com/lit/an/ssya002c/ssya002c.pdf

more details and interesting facts later....

- Bharat Singh | rathorebharat

Lock up latches? Common uses?

Stitching of multiple scan chains. (multiple clock domains).
(different clock enable, posedge, negedge).

Automatically generated by the Test compiler for scan chains.

10 tips for successful scan design: part one & two - 2/17/2000 - EDN
http://www.edn.com/article/CA46603.html
http://www.edn.com/article/CA46604.html

www.evaluationengineering.com/archive/articles/0997dft.htm

-- Bharat Singh | rathorebharat

HW:Launch and capture shift clocks for delay tests? double pulse?

This concept is used for finding transition delay (rise fall) faults:
http://www.soccentral.com/results.asp?CatID=488&EntryID=13069

This explains the basics of launch capture and double pulse:
http://www.iec.org/events/2005/euro_designcon/pdf/6-ta1.pdf

Slow speed clock is required to launch (load unload) the scan flops
or chains and then the faster PLL clock is used generate 2 or 3
pulses of at-speed of internal clock (given to scan flops). The data
is then compared. This is the delay test for the chip.

Nice PPT about delay tests with scan (some algorithms).
www.eng.auburn.edu/~xugefu1/D&TSeminar/files/VLSI07.ppt

At-Speed Structural Test:
ieeexplore.ieee.org/iel5/6540/17459/00805810.pdf

- Bharat Singh | rathorebharat

How to make multiple chains work effectively?

Need of compression logic for scan. EDT compactor.
Collectively feeding multiple scan chains in the design.

For basics:
www.mentor.com/products/dft/news/articles/upload/06_TM_test_compression.pdf

Advanced stuff:
www.mentor.com/products/dft/upload/ITC2005_Compressed_Pattern_Diagnosis_30_3.pdf

More test strategies for testing memories:
http://www.elecdesign.com/Articles/Print.cfm?ArticleID=9527

Multiple short scan chains could be connected to single
big scan chain. Only care is required to see if the connection
is done to correct edge triggered scans. Output of one scan chains
becomes input of another scan chain.

Multiple clock domains might require lockup latches for connecting
mutiple smaller scan chains to one scan chain

- Bharat Singh | rathorebharat

Friday, November 24, 2006

SD:Where British and French management differ?

A amulgam of good traits of all management styles is being Roman in Rome.

Excerpts from the below article on internet.
http://www.mngt.waikato.ac.nz/ejrot/cmsconference/2005/proceedings/criticalresearch/Boussebaa.pdf

Upon 'colonizing' firms, the former become cadres. The term 'cadre' originated from the military and, at the beginning of industrialisation, the French firm hierarchy model presented strong similarities with that of the French army (Poirson, 1993: 54).

The term 'cadre' denotes the dominating managerial class, and althoug h graduates from the university system may also establish themselves as cadres, they lack the status and authority of the graduates of the Grandes Écoles. The term 'cadre' differs from the Anglo-Saxon term 'manager' in that the latter focuses on the management of people whereas the former has a more strategic, planning role (Gordon, 1996).

http://www.mngt.waikato.ac.nz/ejrot/cmsconference/2005/proceedings/criticalresearch/Boussebaa.pdf

French management tends to
conform to Trompenaar's (1993) 'Eiffel Tower' model of corporate organisation, whereby French firms tend to be hierarchical, with a rigid, bureaucratic and well-defined division of labour imposed by the upper echelons of the hierarchy (see also Hofstede 1980). State dirigisme is reflected in management in that the latter is characterised by a centralisation of decision-making that is unquestioned, attaching great importance to the principle of the 'Unity of Command' (Fayol, 1970). Thus, French management is based on the principle of control with power concentrated at the top of the hierarchy (Lane, 1994; van der Klink and Mulder, 1995). Cadres are viewed as autocratic, directive. They see the firm as an elite school in which they are the most intelligent and subordinates, therefore, cannot conceivably have valid ideas. Cadres are, therefore, more possessive of their individual autonomy. Their reaction is: "I know my job; if I am controlled, this means they have no confidence in me" (Poirson, 1993). In contrast, British managers attach less importance to being authoritarian and hence have a more participative, democratic managerial style (Lane, 1989: ch. 4).

http://www.mngt.waikato.ac.nz/ejrot/cmsconference/2005/proceedings/criticalresearch/Boussebaa.pdf

Accor: Story of the merger of american and french company

Franck's book details many other experiences in addition to that of Rhone Poulenc. One of the
successes is that of Accor, the hotel chain. It initially got itself into a bad situation by offering the managers of Motel 6, the company it bought out, a handsome benefits package based on maintaining quarterly and yearly profits over a three-year period, by which time the managers on board at the time of acquisition would leave the company. Introducing a theme which runs throughout the book, Franck details this example of "moral hazard" : the American managers of Motel 6 immediately stopped managing in the interests of the shareholder and ran the company solely to increase short-term bottom-line profits to reward themselves with the highest possible bonuses. Capital investment came to a halt, preventive maintenance vanished, rooms were no longer redecorated. In fact, in many motels, the rooms were no longer even swept or cleaned. Regular clients began to prefer to sleep in their cars in the parking lot when faced with the alternative of a louse and rat-ridden room in a Motel 6 which had become known as a hang-out for drug-dealers.

When Accor realised what was happening they sent Georges Le Mener to turn the situation around. He had come to them after leaving vocational school with only a flimsy hotel management certificate. However he had later graduated with honors from the internal Accor training system, one of the best in France. As Guillaume Franck writes in his book, Le Mener arrived at Motel 6 knowing he had confidence in himself, but knowing precious little about the U.S. and even less about the American budget hotel market. He succeeded against all odds. In making a success of Motel 6, Le Mener handsomely paid back the training and confidence Accor senior management had vested in him. Without him Accor would never have made another acquisition in the U.S., but because of him they later purchased Red Roof Inns and they now have more than 10% of the budget hotel market in the U.S.

Accor brings its managers up through a tough corporate university just outside Paris in which the client is king. The company recruits its staff from outside the elite French management schools (les grandes écoles). Pechiney, on the other hand, used the old boy network to a maximum. Pechiney bought American Can in a famously corrupt deal and is a perfect example of all that can go wrong with the French management style. Le Mener bore more of a resemblance to the typical American manager than to any other French manager mentioned in the book. Many of the other French managers mentioned were incapable of functioning six thousand miles away from their "grande école" support networks and they had to be ignominiously repatriated, in a number of cases because their American subordinates
and colleagues perceived so much arrogance that they just couldn't work with them.

- Bharat Singh | rathorebharat

SD:Does Science and Spirituality Converge at 'c' (Speed of Light)?

More story to come later.

- Bharat Singh | Prashanth | rathorebharat

Thursday, November 23, 2006

HW: Remove a component or module from the chip hierarchy?

Any declaration of that component or module should be removed.
Any instantiation of them should be removed. All remaining holes
for the signals travelling should be highlighted.
This task is a bit tedious and complex as it needs to be done at
chip level.

Thanks n Regards,


-- Bharat Singh | rathorebharat

Wednesday, November 15, 2006

HW: Find finer points to verify this simplest protocol?

Ready comes within 4 clock cycles.
Should not miss more than 2 write enables.

Write 'e' transactions or tests for the same.
Write formal verification properties.
Write VHDL or VERILOG testcases.

- Bharat Singh | rathorebharat

HW: Device best solution for 32bit and 64bit restricted interface! (VHDL)

We have a entity or module which has input output interface
of 32bit wide word. This entity or module will instantiate a
memory of 64bit word. Now device best VHDL solution to feed and
receive this 64bit memory using this 32bit restricted interface.

What will be impact on the highest possible speed which this
64bit memory can possibly be used.

Analyze both the cases when input and ouput interface can be
inout or (only input and only output).

What logic needs to be added in between the interface
and the memory?

- Bharat Singh | rathorebharat

Where an SOC consumes power?

Accurate power-analysis techniques support smart SOC-design choices

Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort

Sequense power aware SoC design flow

Power Islands: The Evolving Topology of SoC Power Management

- Bharat Singh | rathorebharat

Algorithms used by BIST? Marching? Others?

- Bharat Singh | rathorebharat

Tuesday, November 14, 2006

Best book for Beginners for VHDL Verilog and Sysnthsis under one Roof?

Douglas Smith (One of the best books) Golden reference

HDL Chip Design : A Practical guide for Designing, Synthesizing and
Simulating ASICs and FPGAs using VHDL or Verilog

by Douglas J. Smith
Publication date: June 1st 1996

http://www.amazon.com/Hdl-Chip-Design-Synthesizing-Simulating/dp/0965193
438

- Bharat Singh | rathorebharat

How to migrate from 'e' to SystemVerilog?

Synopsys Verification Avenue
http://www.synopsys.com/news/pubs/veritb/oct06/va_vol6_iss3_f6.pdf
Or
http://www.synopsys.com/cgi-bin/systemverilog/pdfr1.cgi?file=SystemVeril
og_for_e_Experts_Janick_Bergeron.pdf
Or
http://www.synopsys.com/links/va_oct06.html?BAC-va&Link=Oct06_Issue_SNPS
_Home_Pubs
Or
EE Times: SystemVerilog won't kill 'e,' say proponents
http://www.eetimes.com/showArticle.jhtml?articleID=174400218&printable=t
rue

- Bharat Singh | rathorebharat

What are HDFR in memories? Uses?

[HW] What is meant by scrabling in memories?

What are ring osillators? Their Common Uses?